Clock signals synchronize data signals so they move properly from one stage of logic to the next. Error-free communication of data signals between components of a computing system is critical. Communication error may be caused by many factors.
A minimum-path (i.e. “min-path”) problem occurs if clock signals allow data to race through too many stages of logic. Min-path problems happen because the enabling pulse widths of the clock signal are too large. The problem is exacerbated because the transmittal rates between components in computing systems are effected by variations in the fabrication process for the individual components. Therefore, computing systems are often designed assuming a worst-case transmittal rate even though the actual transmittal rate may be much faster.
A min-path problem can not be solved by slowing down the clock frequency because the enabling pulse widths become even larger. In addition, slowing down the clock frequency would adversely effect computer system performance.
Speeding up the clock frequency could be used to reduce pulse width. However, a maximum-path (i.e. “max-path”) problem might occur because some logic paths require more time to transfer between circuit elements than the amount of time in a clock pulse width. Therefore, circuit elements will close without catching all of the data in the logic path. Max-path communication problems become even more of a concern as the clock speeds for modern computing systems continue to increase.
The problems discussed above can be addressed by incorporating a clock chopper, or shaver, into the computing system. A clock shaver reduces the width of the enabling pulses without changing the frequency of the clock signal.
One drawback with existing computing systems that include clock shavers is that the clock shavers permanently, or continuously, reduce the enabling clock pulse width. The assortment of components in a computing system often communicate with one another at differing rates. Depending on the type of components in the computing system, continuously reducing the enabling clock pulse width may lead to max-path problems within the computing system.
There is a need in the art for a computing system which reduces data communication error. There is also a need for a computing system that selectively shaves the enabling pulse widths in a clock signal.